1. Field of the Invention
The present invention relates generally to transferring and latching of data signals in computers and computing systems generally, and, particularly, to a dynamic-latch-receiver employing a self reset-pointer with a low-voltage input to result in fast and reliable voltage conversion for the latched state.
2. Discussion of the Prior Art
With rapid improvements in computer processor performance, it is not only highly desirable to have main memories with high-density, but also with higher data rates. For example, with ever-increasing system clock rates of the state-of-the-art microprocessors, high band-width DRAM's are required in order to avoid wait states without adding to the complexity of memory hierarchy, e.g., such as when implementing SRAM cache. Prefetch architectures can effectively boost the burst frequency of the DRAM data rates. For example, a "2b" prefetch architecture has been introduced for synchronous DRAM (SDRAM) to boost the data-rate to 200%. It readily follows that a "4b" prefetch architecture may be used for the double data rate SDRAM (DDR SDRAM) to boost the data-rate to 400%. An "8b" prefetch architecture is already used for the Rambus DRAM (RDRAM), realizing data rates of up to 800%.
Regardless of any prefetch architecture, a frequency conversion is required, for example, by multiplexing a plurality of data signals on a bus with slow speed for storage thereof at corresponding registers during a prefetch operation, and then reading the latched data signal sequentially from the registers to a shared bus at a high speed. A typical example of this frequency conversion is the first in first out (FIFO) circuitary comprising a plurality of registers, input pointers, and output pointers. A key design factor in FIFO circuitry is how to fetch the input data to the registers with input pointers and output the data from the registers with output pointers. Thus, there is a strong and potential requirement to design pointers for use in prefetching architecture, in particular FIFO circuitry.
FIG. 1(a) illustrates a static-latch-receiver design architecture 10 providing four input pointer signals 12a,. . .,12d for controlling four respective latch circuits 20a . . . ,20d. The burst data input signals 14a, . . . ,14d on single data-bus 14 are serially sent to the static latch receiver 10 as a burst mode. This static-latch-receiver 10 fetches the input data when the corresponding pointer signal 12a, . . . ,12d is activated (e.g., rises to logic 1). It does, however, require an input level shifter if the input voltage is different from the latched voltage, causing a speed penalty. In general, a static latch-receiver is slower than the dynamic latch-receiver as discussed hereinbelow.
FIGS. 2(a) and 2(b) illustrate a dynamic-latch-receiver architecture 30, which provides the same function provided by the static-latch-receiver architecture 10 of FIGS. 1(a) and 1(b). As shown in FIG. 2(a), the dynamic-latch-receiver architecture 30 includes latch devices 38a, . . . ,38d responsive to a corresponding edge of respective pointer signals 32a, . . . ,32d (FIG. 2(b)) for latching respective input data signals 14a, . . . ,14d from single input line 14. This dynamic-latch-receiver architecture 30 provides the benefit of allowing input of data signals 14 having lower voltages than the latched voltage and, consequently, is faster than the static-latch-receiver. It does, however, result in a problem if a data input, e.g., signals 14a, . . . ,14d, is changed when the pointer signal is active, requiring a pointer signal of smaller pulse-width. In general, transferring a small pulse pointer signal globally is difficult, since the wiring carrying such global small pulse pointer signals exhibits RC low pass filter effects, which severely degrades the signal. The precharge signals 34a, . . . ,34d precharges a respective latched node 38a, . . . ,38d before the signal input data on serial data bus 14 is stored in the corresponding latched node 38a, . . . ,38d as in a conventional dynamic logic.
It would thus be highly desirable to provide an improved circuit architecture implementing pointer signals that enable high-speed, dynamic latching of data signals carried serially on a single line to one or more latches sequentially, in a simple and efficient manner.